Name
Abstract | ||
|---|---|---|
The recently introduced Split-Row Threshold algorithm significantly improves the error performance when compared to the non- threshold Split-Row algorithm while requiring a very small increase in hardware complexity. The Multi-Split-Row Threshold decoding algorithm presented in this paper enables further reductions in routing complexity for greater throughput and smaller circuit area implementations. Several Multi-Split-Row Threshold decoder designs have been implemented in 65 nm CMOS and the impact of the different levels of partitioning on error performance, wire interconnect complexity, decoder area, and speed are investigated. The Split-Row-16 Threshold decoder occupies 3.8 mm2, runs at 100 MHz, delivers a throughput of 13.8 Gbps at 15 iterations and is only 0.28 dB and 0.22 dB away from SPA and MinSum Normalized. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISCAS.2009.5118296 | Taipei |
Keywords | Field | DocType |
decoding,parity check codes,CMOS,LDPC codes,decoder area,error performance,frequency 100 MHz,hardware complexity,multisplit-row threshold decoding,nonthreshold split-row algorithm,routing complexity,wire interconnect complexity | Computer science,Low-density parity-check code,Parallel computing,CMOS,Electronic engineering,Soft-decision decoder,Decoding methods,Throughput,Digital Video Broadcasting,Interconnection,Message passing | Conference |
ISBN | Citations | PageRank |
978-1-4244-3828-0 | 13 | 0.93 |
References | Authors | |
12 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tinoosh Mohsenin | 1 | 406 | 47.43 |
| Dean Nguyen Truong | 2 | 13 | 0.93 |
| Bevan M. Baas | 3 | 295 | 27.78 |