Name
Title | ||
|---|---|---|
NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging |
Abstract | ||
|---|---|---|
As the number of transistors that are integrated onto a silicon die continues to increase, the compute power is becoming a commodity. This has enabled a whole host of new applications that rely on high-throughput computations. Recently, the need for faster and cost-effective applications in form-factor constrained environments has driven an interest in on-chip acceleration of algorithms based on Monte Carlo simulations. Though Field Programmable Gate Arrays (FPGAs), with hundreds of on-chip arithmetic units, show significant promise for accelerating these embarrassingly parallel simulations, a challenge exists in sharing access to simulation data among many concurrent experiments. This paper presents a compute architecture for accelerating Monte Carlo simulations based on the Network-on-Chip (NOC) paradigm for on-chip communication. We demonstrate through the complete implementation of a Monte Carlo-based image reconstruction algorithm for Single-Photon Emission Computed Tomography (SPECT) imaging that this complex problem can be accelerated by two orders of magnitude on even a modestly sized FPGA over a 2 GHz Intel Core 2 Duo Processor. The architecture and the methodology that we present in this paper is modular and hence it is scalable to problem instances of different sizes, with application to other domains that rely on Monte Carlo simulations. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TC.2011.250 | Computers, IEEE Transactions |
Keywords | Field | DocType |
Monte Carlo methods,digital arithmetic,field programmable gate arrays,image reconstruction,medical image processing,network-on-chip,single photon emission computed tomography,transistors,Intel Core 2 Duo Processor,Monte Carlo simulations,Monte Carlo-based image reconstruction algorithm,NOC paradigm,NoC-based FPGA acceleration,SPECT imaging,concurrent experiments,field programmable gate arrays,form-factor constrained environments,high-throughput computations,network-on-chip paradigm,on-chip acceleration,on-chip arithmetic units,on-chip communication,parallel simulations,silicon die,single-photon emission computed tomography imaging,transistors,Monte Carlo (MC) simulation,Network-on-chip (NoC),field-programmable gate-array (FPGA),nuclear medical imaging,single-photon emission computed tomography (SPECT) | Iterative reconstruction,Monte Carlo method,System on a chip,Computer science,Parallel computing,Embarrassingly parallel,Field-programmable gate array,Network on a chip,Spect imaging,Scalability | Journal |
Volume | Issue | ISSN |
62 | 3 | 0018-9340 |
Citations | PageRank | References |
3 | 0.60 | 10 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Phillip Kinsman | 1 | 4 | 0.98 |
| Nicola Nicolici | 2 | 807 | 59.91 |