Name
Title | ||
|---|---|---|
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements |
Abstract | ||
|---|---|---|
This work presents the analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. Jitter accumulation in phase frequency detector degrades the accuracy of on-chip jitter measurements, and required to be mitigated. In order to estimate the jitter accumulation in phase frequency detectors, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that, with a 50 mV power supply noise injection, jitter accumulation can be reduced from 1.03 ps to 0.49 ps (52% reduction) by using an interleaved architecture. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISOCC.2011.6138668 | ISOCC |
Keywords | DocType | ISBN |
cmos integrated circuits,jitter,cmos technology,spice simulation,high-accuracy on-chip jitter measurements,interleaved phase frequency detectors,jitter accumulation,bist,pll,design for testability,on-chip measurement,chip | Conference | 978-1-4577-0710-0 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masato Sakurai | 1 | 24 | 4.16 |
| Kiichi Niitsu | 2 | 126 | 38.14 |
| Naohiro Harigai | 3 | 6 | 2.58 |
| Daiki Hirabayashi | 4 | 3 | 1.47 |
| daiki oki | 5 | 2 | 0.75 |
| Takahiro J. Yamaguchi | 6 | 34 | 4.61 |
| Haruo Kobayashi | 7 | 38 | 25.15 |