Name
Abstract | ||
|---|---|---|
We present an improved thresholding LDPC decoding algorithm which outperforms the Split-Row and original Split-Row Threshold decoders with a small increase in hard-ware. Simulation results show that the algorithm provides 0.27- 0.50 dB coding gain over Split-Row, 0.10-0.20 dB over Split-Row Threshold, and is within 0.08-0.13 dB of SPA. Compared with the original Threshold algorithm the check node processor's gate count is increased by 3% while total chip area is kept the same. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICC.2009.5198733 | Dresden |
Keywords | Field | DocType |
decoding,parity check codes,LDPC codes,check node processor gate,low density parity check code,split-row threshold decoding algorithm | Coding gain,Gate count,Algorithm design,Low-density parity-check code,Computer science,Algorithm,Chip,CMOS,Real-time computing,Thresholding,Decoding methods | Conference |
ISSN | ISBN | Citations |
1938-1883 E-ISBN : 978-1-4244-3435-0 | 978-1-4244-3435-0 | 5 |
PageRank | References | Authors |
0.61 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tinoosh Mohsenin | 1 | 406 | 47.43 |
| Dean Truong | 2 | 34 | 2.48 |
| Bevan M. Baas | 3 | 295 | 27.78 |