Name
Abstract | ||
|---|---|---|
This brief presents an efficient complex event-processing framework, designed to process a large number of sequential events on field-programmable gate arrays (FPGAs). Unlike conventional structured query language based approaches, our approach features logic automation constructed with a new C-based event language that supports regular expressions on the basis of C functions, so that a wide variety of event-processing applications can be efficiently mapped to FPGAs. Evaluations on an FPGA-based network interface card show that we can achieve 12.3 times better event-processing performance than does a CPU software in a financial trading application. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2197230 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
C language,field programmable gate arrays,formal languages,high level synthesis,logic design,network interfaces,reconfigurable architectures,sequential circuits,C functions,C-based complex event processing,C-based event language,CPU software,FPGA-based network interface card,conventional structured query language,event-processing applications,event-processing performance,field-programmable gate arrays,financial trading application,logic automation,reconfigurable hardware,regular expressions,sequential events,Circuit synthesis,computer languages,pipeline processing,reconfigurable architectures | Logic synthesis,Computer science,FpgaC,Real-time computing,Electronic engineering,Hardware description language,Programmable logic device,Computer architecture,High-level synthesis,Field-programmable gate array,Complex event processing,Reconfigurable computing,Embedded system | Journal |
Volume | Issue | ISSN |
21 | 5 | 1063-8210 |
Citations | PageRank | References |
1 | 0.44 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroaki Inoue | 1 | 312 | 39.57 |
| Takashi Takenaka | 2 | 37 | 7.74 |
| Masato Motomura | 3 | 91 | 27.81 |