Name
Abstract | ||
|---|---|---|
In common design flows of mixed-signal ASICs, the transition from system-level models to implementation-level models is executed in a manual process that carries potential for an efficiency gain by automation. This contribution addresses this aspect by showing and discussing an approach for efficient automated transitions from digital parts of Simulink models representing heterogeneous systems to VHDL and Verilog descriptions. It describes a design flow, in which a Simulink model representing a digital part of a mixed-signal ASIC is checked and optimized for automated generation of design rule compliant and more efficient digital hardware implementations. For this purpose, modeling guidelines and optimizations were implemented and integrated into an easily usable graphical user interface. Thereby, the strategy is based on considering and optimizing the digital part with respect to the surrounding heterogeneous system. An evaluation of the presented design flow is shown by applying the flow to an automotive hardware design. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/DDECS.2012.6219090 | Design and Diagnostics of Electronic Circuits & Systems |
Keywords | Field | DocType |
application specific integrated circuits,hardware description languages,integrated circuit design,VHDL,Verilog descriptions,automotive mixed-signal ASIC,efficient digital design,implementation-level models,simulink | Computer science,Design flow,Real-time computing,Electronic engineering,Integrated circuit design,VHDL,Physical design,Verilog,Register-transfer level,Hardware description language,Embedded system,Electronic circuit design | Conference |
ISSN | ISBN | Citations |
2334-3133 | 978-1-4673-1186-1 | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andreas Mauderer | 1 | 0 | 0.34 |
| Marvin Freier | 2 | 0 | 0.34 |
| Jan-Hendrik Oetjens | 3 | 6 | 1.57 |
| W. Rosenstiel | 4 | 15 | 4.15 |