Name
Abstract | ||
|---|---|---|
We present the details of our energy-efficient asynchronous floating-point multiplier (FPM). We discuss design trade-offs of various multiplier implementations. A higher radix array multiplier design with operand-dependent carry-propagation adder and low handshake overhead pipeline design is presented, which yields significant energy savings while preserving the average throughput. Our FPM also includes a hardware implementation of denormal and underflow cases. When compared against a custom synchronous FPM design, our asynchronous FPM consumes 3X less energy per operation while operating at 2.3X higher throughput. To our knowledge, this is the first detailed design of a high-performance asynchronous IEEE-754 compliant double-precision floating-point multiplier. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ASYNC.2012.19 | Asynchronous Circuits and Systems |
Keywords | Field | DocType |
IEEE standards,adders,asynchronous circuits,floating point arithmetic,custom synchronous FPM design,denormal cases,energy savings,energy-efficient asynchronous floating-point multiplier,floating-point arithmetic,hardware implementation,high-performance IEEE-754 compliant double-precision multiplier,low handshake overhead pipeline design,operand-dependent carry-propagation adder,radix array multiplier design,underflow cases,Floating point arithmetic,asynchronous logic circuits,pipeline processing,very-large-scale integration | Asynchronous communication,Arithmetic underflow,Denormal number,Adder,Computer science,Floating point,Parallel computing,Multiplier (economics),Throughput,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1522-8681 | 978-1-4673-1360-5 | 4 |
PageRank | References | Authors |
0.46 | 14 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Basit Riaz Sheikh | 1 | 4 | 0.46 |
| Rajit Manohar | 2 | 1038 | 96.72 |