| A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic | 0 | 0.34 | 2022 |
| HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces | 0 | 0.34 | 2022 |
| General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs | 0 | 0.34 | 2022 |
| Hardware/software Co-design for Neuromorphic Systems | 0 | 0.34 | 2022 |
| Zerializer - towards zero-copy serialization. | 3 | 0.38 | 2021 |
| Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures | 0 | 0.34 | 2021 |
| Hierarchical Token Rings for Address-Event Encoding | 0 | 0.34 | 2021 |
| Balancing Specialized Versus Flexible Computation in Brain–Computer Interfaces | 1 | 0.35 | 2021 |
| An Open-Source EDA flow for Asynchronous Logic | 1 | 0.35 | 2021 |
| Hardware-Software Co-Design for Brain-Computer Interfaces | 2 | 0.35 | 2020 |
| Dali - A Gridded Cell Placement Flow. | 0 | 0.34 | 2020 |
| Shared-Staticizer for Area-Efficient Asynchronous Circuits | 0 | 0.34 | 2020 |
| Exact Timing Analysis for Asynchronous Circuits With Multiple Periods | 0 | 0.34 | 2020 |
| Cyclone: A Static Timing and Power Engine for Asynchronous Circuits | 0 | 0.34 | 2020 |
| A Systematic Approach for Arbitration Expressions | 0 | 0.34 | 2020 |
| AMC: An Asynchronous Memory Compiler | 0 | 0.34 | 2019 |
| Self-Timed Adaptive Digit-Serial Addition | 1 | 0.40 | 2019 |
| Operation-Dependent Frequency Scaling Using Desynchronization | 0 | 0.34 | 2019 |
| Asynchronous Signalling Processes | 1 | 0.36 | 2019 |
| QDI Constant-Time Counters. | 1 | 0.40 | 2019 |
| Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model. | 11 | 0.78 | 2019 |
| SPRoute: A Scalable Parallel Negotiation-based Global Router | 0 | 0.34 | 2019 |
| A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption. | 2 | 0.37 | 2018 |
| The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. | 2 | 0.39 | 2018 |
| Exact Timing Analysis for Asynchronous Systems. | 2 | 0.45 | 2018 |
| Energy-Efficient Hybrid Cmos-Nems Lif Neuron Circuit In 28 Nm Cmos Process | 0 | 0.34 | 2017 |
| Design of tunable digital delay cells | 0 | 0.34 | 2017 |
| Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. | 6 | 0.45 | 2017 |
| The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits | 3 | 0.42 | 2017 |
| On Using Time Without Clocks via Zigzag Causality. | 1 | 0.35 | 2017 |
| Gradual Synchronization. | 1 | 0.36 | 2016 |
| Comparing Stochastic and Deterministic Computing | 2 | 0.39 | 2015 |
| TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip | 130 | 4.00 | 2015 |
| AES Hardware-Software Co-design in WSN | 2 | 0.46 | 2015 |
| Timing Driven Placement for Quasi Delay-Insensitive Circuits | 3 | 0.41 | 2015 |
| Analyzing Isochronic Forks with Potential Causality | 5 | 0.54 | 2015 |
| Design Of A Qdi Asynchronous Aer Serializer/Deserializer Link In 180nm For Event-Based Sensors For Robotic Applications | 0 | 0.34 | 2015 |
| Preventing glitches and short circuits in high-level self-timed chip specifications | 0 | 0.34 | 2015 |
| Removing concurrency for rapid functional verification | 0 | 0.34 | 2014 |
| Using asymmetric cores to reduce power consumption for interactive devices with bi-stable displays | 0 | 0.34 | 2014 |
| Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with ~100× speedup in time-to-solution and ~100,000× reduction in energy-to-solution | 4 | 0.56 | 2014 |
| An asymmetric dual-processor architecture for low-power information appliances | 4 | 0.44 | 2014 |
| Low Power Asynchronous VLSI with NEM Relays | 2 | 0.39 | 2014 |
| A memory-efficient routing method for large-scale spiking neural networks. | 6 | 0.49 | 2013 |
| cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells | 9 | 0.72 | 2013 |
| Inverting Martin Synthesis for Verification | 2 | 0.39 | 2013 |
| A Bit of Analysis on Self-Timed Single-Bit On-Chip Links | 1 | 0.38 | 2013 |
| An Asynchronous Floating-Point Multiplier | 4 | 0.46 | 2012 |
| Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels. | 2 | 0.40 | 2012 |
| A Low Power Asynchronous GPS Baseband Processor | 10 | 0.63 | 2012 |
