Name
Abstract | ||
|---|---|---|
This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ACSD.2012.29 | Application of Concurrency to System Design |
Keywords | Field | DocType |
asynchronous circuits,delays,dual codes,error correction codes,error detection codes,fault diagnosis,fault tolerance,integrated circuit interconnections,logic design,4-phase dual rail code,GALS-systems,asynchronous circuit design,coding efficiency,data transmission,data word processing,delay-insensitive code,error correcting codes,error detecting codes,fault model,fault tolerance,four-phase dual-rail coding,information redundancy,interconnect architecture,interconnect resource,metastable upset,robust asynchronous interfacing scheme,single-bit errors,system timing,variation tolerance,Asynchronous circuits,Delay-insensitivity,Error correcting codes,Fault-tolerance,GALS,Metastability | Asynchronous communication,Data transmission,Computer science,Low-density parity-check code,Interfacing,Real-time computing,Theoretical computer science,Robustness (computer science),Fault tolerance,Word (computer architecture),Fault model | Conference |
ISSN | ISBN | Citations |
1550-4808 | 978-1-4673-1687-3 | 3 |
PageRank | References | Authors |
0.43 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jakob Lechner | 1 | 13 | 3.88 |
| Martin Lampacher | 2 | 3 | 0.43 |
| Thomas Polzer | 3 | 49 | 8.43 |