Name
Title | ||
|---|---|---|
Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture |
Abstract | ||
|---|---|---|
In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments with the prototyped IC and by Spice simulation. The simulation results show that an open defect can be detected within 10nsec which generates only additional delay of 0.7nsec. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/3DIC.2012.6262968 | 3D Systems Integration Conference |
Keywords | DocType | ISBN |
IEEE standards,SPICE,integrated circuit design,integrated circuit interconnections,integrated circuit testing,three-dimensional integrated circuits,3D IC interconnects,IEEE 1149.1 architecture,Spice simulation,defective interconnects,open defects detection,supply current testing,testable IC design,testable design method,time 10 ns | Conference | 978-1-4673-2189-1 |
Citations | PageRank | References |
5 | 0.48 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomoaki Konishi | 1 | 5 | 0.48 |
| Hiroyuki Yotsuyanagi | 2 | 70 | 19.04 |
| Masaki Hashizume | 3 | 98 | 27.83 |