Name
Abstract | ||
|---|---|---|
Energy-recovering schemes have been proposed in the literature as an alternative approach to low-power design, while their performance has been demonstrated to be extremely promising when driving large capacitive loads, such as clock distribution networks. This work investigates the potential of the energy-recovering methodology for improving the energy efficiency of through-silicon via (TSV) interconnects in 3D ICs. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/3DIC.2009.5306581 | San Francisco, CA |
Keywords | Field | DocType |
clocks,distribution networks,integrated circuit design,integrated circuit interconnections,low-power electronics,monolithic integrated circuits,capacitive loads,clock distribution network,energy efficiency,energy-recovering interconnects,low-power 3D stacked IC,low-power design,through-silicon via interconnects | Capacitance,Efficient energy use,Dissipation,Distribution networks,CMOS,Electronic engineering,Capacitive sensing,Integrated circuit design,Engineering,Electrical engineering,Low-power electronics | Conference |
ISSN | ISBN | Citations |
2164-0157 | 978-1-4244-4512-7 | 0 |
PageRank | References | Authors |
0.34 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Panagiotis Asimakopoulos | 1 | 0 | 0.34 |
| Geert Van der Plas | 2 | 0 | 0.68 |
| Alex Yakovlev | 3 | 0 | 0.34 |
| Paul Marchal | 4 | 0 | 0.34 |