Name
Abstract | ||
|---|---|---|
The implementation of debugging tools through joint action test group (JTAG) has led to increased exposure of intellectual property through the interface. In this brief, the first hardware implementation of a flexible multilevel access security system for the JTAG interface is detailed. The proposed method is user-privilege aware, which allows for higher granularity for controlling user access of individual scan chains. The loading of individual JTAG instructions into scan chains can be blocked based on the credentials of the user. The hardware modifications proposed are compliant with IEEE 1149.1, have minimal timing overhead, and require no modifications to the core logic of the integrated circuit. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2208209 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
IEEE standards,authorisation,industrial property,program debugging,program testing,software architecture,IEEE 1149.1,JTAG instruction,JTAG interface,debugging tool,flexible multilevel access security system,hardware implementation,hardware modification,intellectual property,joint action test group system,scan chain,secure architecture,timing overhead,user access,user-privilege aware,Boundary scan,joint action test group (JTAG),security,testing | Boundary scan,Boundary scan description language,Authentication,Computer science,Scan chain,Real-time computing,Software architecture,Granularity,Integrated circuit,Embedded system,Debugging | Journal |
Volume | Issue | ISSN |
21 | 7 | 1063-8210 |
Citations | PageRank | References |
14 | 1.04 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luke Pierce | 1 | 14 | 1.04 |
| Spyros Tragoudas | 2 | 625 | 88.87 |