Name
Abstract | ||
|---|---|---|
Low voltage operated embedded SRAMs in nanometric CMOS technologies are sensitive to PVT variations and hence can cause poor yield. In this paper, we exploit the concept of Dynamic Noise Margin (DNM) to enhance the 6TSRAM cell design flexibility and reliability. In particular, a transition Word-line driver (WL) boost circuit design is proposed. Carried-out post layout Monte Carlo simulations on a 400 mV, 4 Kbit 6T SRAM sub array in TSMC 65nm CMOS technology show the benefit of proposed scheme. A 28.5% improvement in the developed bitline differential voltage and a 39% reduction in cell leakage current are achieved. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MWSCAS.2012.6291950 | Circuits and Systems |
Keywords | Field | DocType |
cmos memory circuits,monte carlo methods,sram chips,circuit reliability,network synthesis,6t-sram,dnm,monte carlo simulations,pvt variations,tsmc,boost circuit design,dynamic noise margin,low operating voltage,nanometric cmos technologies,reliability,transition word-line driver,word-line boost driver design,sram reliability,word-line boost,yield,low leakage,low voltage,transistors,leakage current,cmos integrated circuits | Boost converter,Leakage (electronics),Computer science,Voltage,Circuit reliability,Static random-access memory,CMOS,Electronic engineering,Low voltage,Noise margin | Conference |
ISSN | ISBN | Citations |
1548-3746 E-ISBN : 978-1-4673-2525-7 | 978-1-4673-2525-7 | 3 |
PageRank | References | Authors |
0.46 | 5 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shakir, T. | 1 | 3 | 0.46 |
| Manoj Sachdev | 2 | 669 | 88.45 |