Paper Info
Title
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA
Abstract
A compact lookup table (LUT) circuit using spin transfer-torque magnetic tunnel junction (STT-MTJ) devices combined with MOS transistors is proposed for a standby-power-free field-programmable gate array (FPGA). Since STT-MTJ devices essentially have an asymmetric characteristic in switching currents, one of two write-control transistors can be implemented with a small feature size, while the width of the other one is still large. By sharing the large size of write-control transistor, almost all the transistor size in the proposed LUT circuit becomes small. In fact, the effective silicon area of the proposed write-control transistors for a 6-input LUT circuit is reduced to 68 % in comparison with that of a conventional nonvolatile LUT circuit without applying the asymmetric transistor sizing.
Year
DOI
Venue
2012
10.1109/MWSCAS.2012.6292025
Circuits and Systems
Keywords
Field
DocType
mosfet,field programmable gate arrays,logic design,magnetic tunnelling,table lookup,6-input lut circuit,mos transistors,mtj current switching asymmetry,stt-mtj devices,area-efficient lut circuit design,area-efficient lookup table circuit design,asymmetric transistor sizing,nonvolatile fpga,spin transfer-torque magnetic tunnel junction devices,standby-power- free fpga,standby-power-free field-programmable gate array,write-control transistors,cmos integrated circuits,logic gates,nonvolatile memory,transistors
Lookup table,Logic gate,Computer science,Circuit design,CMOS,Electronic engineering,Gate array,Non-volatile memory,Transistor,MOSFET,Electrical engineering
Conference
ISSN
ISBN
Citations 
1548-3746 E-ISBN : 978-1-4673-2525-7
978-1-4673-2525-7
3
PageRank 
References 
Authors
0.46
7
3
Name
Order
Citations
PageRank
Daisuke Suzuki1477.32
Natsui, M.251.57
Takahiro Hanyu344178.58