Name
Abstract | ||
|---|---|---|
A 148ps, single-cycle 64-bit Ling adder with Constant-Delay (CD) logic implemented in the critical path is fabricated in a 65nm, 1V CMOS process. The pre-evaluation and constant delay (regardless of the logic expressions) features of CD logic makes it up to 2X faster than dynamic logic in realizing complex logic functions such as addition. At 1V supply, this adder's worst-case measured power and leakage power are 135mW and 0.22mW, respectively. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/CICC.2012.6330709 | Custom Integrated Circuits Conference |
Keywords | Field | DocType |
CMOS logic circuits,adders,CD logic,CMOS process,complex logic functions,constant delay,constant-delay logic,critical path,dynamic logic,logic expressions,power 135 mW,single-cycle Ling adder,size 65 nm,word length 64 bit | Logic gate,Pass transistor logic,Adder,Computer science,Logic optimization,AND-OR-Invert,Electronic engineering,Logic level,Logic family,Dynamic logic (digital electronics) | Conference |
ISSN | ISBN | Citations |
0886-5930 E-ISBN : 978-1-4673-1554-8 | 978-1-4673-1554-8 | 0 |
PageRank | References | Authors |
0.34 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chuang, P.I.-J. | 1 | 4 | 0.90 |
| David Li | 2 | 0 | 0.34 |
| Manoj Sachdev | 3 | 669 | 88.45 |
| Vincent C. Gaudet | 4 | 66 | 5.62 |