Name
Title | ||
|---|---|---|
On the automatic integration of hardware accelerators into FPGA-based embedded systems |
Abstract | ||
|---|---|---|
This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/FPL.2012.6339218 | Field Programmable Logic and Applications |
Keywords | Field | DocType |
XML,application program interfaces,electronic design automation,embedded systems,field programmable gate arrays,hardware-software codesign,software architecture,FPGA-based embedded systems,HW-SW partitioning,OpenMP-based application,XML file,automatic framework,automatic hardware accelerator integration,hardware-software partitioning,scheduling code,software architecture,synchronization code | Scheduling (computing),Computer science,Resource-oriented architecture,Computer hardware,Synchronization,Computer architecture,XML,Parallel computing,Field-programmable gate array,Electronic design automation,Software architecture,Hardware architecture,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4673-2255-3 | 7 | 0.59 |
References | Authors | |
7 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christian Pilato | 1 | 329 | 32.19 |
| Cazzaniga, A. | 2 | 19 | 2.46 |
| Durelli, G. | 3 | 20 | 2.12 |
| Otero, A. | 4 | 8 | 0.95 |