| HOLL: Program Synthesis for Higher Order Logic Locking | 1 | 0.37 | 2022 |
| A Composable Design Space Exploration Framework to Optimize Behavioral Locking | 0 | 0.34 | 2022 |
| ASSURE: RTL Locking Against an Untrusted Foundry | 1 | 0.35 | 2021 |
| Cicero: A Domain-Specific Architecture For Efficient Regular Expression Matching | 1 | 0.35 | 2021 |
| From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics | 0 | 0.34 | 2021 |
| Automatic Generation of Heterogeneous SoC Architectures with Secure Communications | 0 | 0.34 | 2021 |
| Agile SoC Development with Open ESP - Invited Paper. | 0 | 0.34 | 2020 |
| CAD-Base: An Attack Vector into the Electronics Supply Chain | 2 | 0.37 | 2019 |
| High-Level Synthesis Of Benevolent Trojans | 0 | 0.34 | 2019 |
| TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking | 4 | 0.43 | 2019 |
| Black-Hat High-Level Synthesis: Myth or Reality? | 1 | 0.35 | 2019 |
| DarkMem: Fine-grained power management of local memories for accelerators in embedded systems. | 0 | 0.34 | 2018 |
| Securing Hardware Accelerators: A New Challenge for High-Level Synthesis. | 0 | 0.34 | 2018 |
| The Case for Polymorphic Registers in Dataflow Computing. | 1 | 0.36 | 2018 |
| Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis. | 0 | 0.34 | 2018 |
| Bridging the Gap Between Software and Hardware Designers Using High-Level Synthesis. | 0 | 0.34 | 2017 |
| System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip | 3 | 0.38 | 2017 |
| Performance Estimation of Task Graphs Based on Path Profiling | 0 | 0.34 | 2016 |
| Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip | 2 | 0.38 | 2016 |
| Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs | 1 | 0.36 | 2016 |
| An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems. | 6 | 0.48 | 2016 |
| A Survey and Evaluation of FPGA High-Level Synthesis Tools | 74 | 2.96 | 2016 |
| On the design of scalable and reusable accelerators for big data applications. | 3 | 0.38 | 2016 |
| Editorial: Special Issue on Innovative Design Methods for Smart Embedded Systems | 4 | 0.41 | 2016 |
| Effective Reconfigurable Design: The FASTER Approach. | 0 | 0.34 | 2014 |
| PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures | 8 | 0.62 | 2014 |
| A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces | 3 | 0.42 | 2014 |
| Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration | 0 | 0.34 | 2014 |
| A design methodology for compositional high-level synthesis of communication-centric SoCs | 8 | 0.50 | 2014 |
| Runtime adaptation on dataflow HPC platforms | 6 | 0.66 | 2013 |
| A Framework For Effective Exploitation Of Partial Reconfiguration In Dataflow Computing | 0 | 0.34 | 2013 |
| Bambu: A Modular Framework For The High Level Synthesis Of Memory-Intensive Applications | 12 | 0.67 | 2013 |
| Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems | 2 | 0.37 | 2013 |
| A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs. | 2 | 0.36 | 2013 |
| SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs | 2 | 0.46 | 2013 |
| Dataflow Computing With Polymorphic Registers | 0 | 0.34 | 2013 |
| D-Recs: A Complete Methodology To Implement Self Dynamic Reconfigurable Fpga-Based Systems | 1 | 0.34 | 2013 |
| A2B: An integrated framework for designing heterogeneous and reconfigurable systems | 2 | 0.43 | 2013 |
| A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications | 0 | 0.34 | 2013 |
| On the automatic integration of hardware accelerators into FPGA-based embedded systems | 7 | 0.59 | 2012 |
| On the Development of a Runtime Reconfigurable Multicore System-on-Chip | 3 | 0.43 | 2012 |
| Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration | 1 | 0.35 | 2012 |
| TaBit: A framework for task graph to bitstream generation | 0 | 0.34 | 2012 |
| Automatic run-time manager generation for reconfigurable MPSoC architectures | 7 | 0.58 | 2012 |
| An open-source design and validation platform for reconfigurable systems | 3 | 0.48 | 2012 |
| FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration | 6 | 0.48 | 2012 |
| Smart technologies for effective reconfiguration: The FASTER approach | 4 | 0.41 | 2012 |
| Evaluating Static CMOS Complex Cells in Technology Mapping. | 0 | 0.34 | 2011 |
| A runtime adaptive controller for supporting hardware components with variable latency | 10 | 0.88 | 2011 |
| SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. | 0 | 0.34 | 2011 |
