Name
Title | ||
|---|---|---|
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm |
Abstract | ||
|---|---|---|
This paper describes energy efficient and reconfigurable fused/continuous Multiply-Accumulator (MAC) architecture for single-precision Floating-point and 16-bit signed integer operands. This eight-stage pipelined and single-cycle throughput MAC design contains a bit level pipelined multiplier, followed by fast sparse-tree adder and single cycle accumulator loop with delayed normalization logic. Operation driven energy control is achieved using dynamic clock and fine grained power gating techniques. Power gating is employed in 98% of design to save 79% of leakage power in idle mode, at 1.2 V supply and 110 C. The use of fully shared logic in the multiplier, accumulator and normalization blocks for different operations enables a compact design of 0.54 mm2 containing 117 K transistors in eight-metal 65 nm CMOS technology. The 15-FO4 design provides 6.8 GFLOPS of performance with total energy efficiency of 90 mW/GFLOP at 1.2V and 3.4 GHz operation. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/VLSI.Design.2010.59 | VLSI Design |
Keywords | Field | DocType |
CMOS logic circuits,floating point arithmetic,logic design,microprocessor chips,CMOS technology,bit level pipelined multiplier,delayed normalization logic,dynamic clock,eight-stage pipelined MAC design,fast sparse-tree adder,fine grained power gating techniques,floating-point operands,frequency 3.4 GHz,fully shared logic,operation driven energy control,power 90 mW,reconfigurable fused/continuous multiply-accumulator architecture,signed integer operands,single cycle accumulator loop,single-cycle throughput MAC design,size 65 nm,temperature 110 C,voltage 1.2 V,word length 16 bit,Floating-point,Fused and continuous MAC,VLSI,multiply-accumulate | Logic synthesis,Adder,Computer science,Floating point,Parallel computing,Multiplier (economics),Electronic engineering,Real-time computing,CMOS,Power gating,Very-large-scale integration,Accumulator (structured product) | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-4244-5541-6 | 7 |
PageRank | References | Authors |
0.57 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shailendra Jain | 1 | 429 | 43.48 |
| Erraguntla, V. | 2 | 7 | 0.57 |
| Sriram R. Vangal | 3 | 1857 | 114.54 |
| Yatin Hoskote | 4 | 1234 | 85.97 |