Name
Abstract | ||
|---|---|---|
The paper presents the design and realization of frequency synthesizer based on a phase-locked loop together with frequency-doubling and fractional phase-rotating techniques. To achieve lower power design, a current-reused technique is employed on the combiner of quadrature voltage-controlled oscillator and frequency doubler and the other combiner of injection-lock frequency divider and phase rotator. The synthesizer provides the tuning range of 21.2 to 22.4 GHz and dissipates 28 mW. The measured phase noise is -106.7 dBc/Hz from 1-MHz offset. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCIT.2012.6380873 | ISCIT |
Keywords | Field | DocType |
cmos integrated circuits,mmic frequency convertors,mmic oscillators,field effect mmic,frequency dividers,frequency multipliers,frequency synthesizers,low-power electronics,phase locked loops,phase noise,voltage-controlled oscillators,cmos technology,current-reused technique,fractional phase rotating technique,frequency 21.2 ghz to 22.4 ghz,frequency doubling,injection-lock frequency divider,low-power frequency synthesizer,phase rotator,phase-locked loop,power 28 mw,quadrature voltage-controlled oscillator,size 0.18 mum,low power electronics | Phase-locked loop,Frequency divider,Variable-frequency oscillator,Computer science,Phase noise,Voltage-controlled oscillator,Frequency synthesizer,Frequency multiplier,Electrical engineering,Direct digital synthesizer | Conference |
ISBN | Citations | PageRank |
978-1-4673-1155-7 | 0 | 0.34 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Jia-Jiun Lin | 2 | 0 | 0.34 |
| Chih-Hsiang Chang | 3 | 0 | 0.68 |