Name
Abstract | ||
|---|---|---|
A noise-shaped pipelined ADC is presented in this paper. A minimal complexity ΔΣ modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18- μm CMOS, the ADC achieves 12 ENOB with 64-MHz clock at 6× OSR while using only a 9-b linear front-end multiplying DAC. The delta-sigma sub-ADCs dissipate 400 μW of extra power (out of 13.9-mW total power) while significantly enhancing the overall ADC linearity. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2012.2227605 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
CMOS integrated circuits,analogue-digital conversion,circuit feedback,delta-sigma modulation,CMOS process,analog imperfections,delta-sigma subADC,frequency 64 MHz,high-order noise shaping,highly linear noise-shaped pipelined ADC,linear front-end multiplying DAC,minimal complexity ΔΣ modulator,power 13.9 mW,power 400 muW,relaxed accuracy front-end,residue feedback,size 0.18 mum,$Delta Sigma$ modulation,feedback DAC,loop filter,noise shaping,oversampling converters,pipelined ADCs,switched-capacitor circuits | Control theory,Computer science,Linearity,Switched capacitor,Modulation,CMOS,Electronic engineering,Delta-sigma modulation,Effective number of bits,Noise shaping,Successive approximation ADC | Journal |
Volume | Issue | ISSN |
48 | 2 | 0018-9200 |
Citations | PageRank | References |
4 | 0.47 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Omid Rajaee | 1 | 29 | 3.25 |
| Un-Ku Moon | 2 | 836 | 140.98 |