Paper Info
Title
TaBit: A framework for task graph to bitstream generation
Abstract
Nowadays, the usual embedded design flow makes use of different tools to perform the several steps required to obtain a running application on a reconfigurable platform. The integration among these tools is usually not fully automated, forcing the developer to take care of these intermediate steps. This process slows down the application development and delays its time to market. In this work we present the TaBit framework, intended for FPGA designers, that is able to guide the developer from the original partitioned application, described as a task graph, down to its deployment onto the target device. Moreover, this framework defines a set of interfaces that allows the developer to integrate custom scheduling and floor placing techniques. The framework takes care of the integration between the different steps and, based on the designer inputs, it is able to automatically generate a software Scheduling Engine and the set of bitstreams ready to be deployed onto the target device.
Year
DOI
Venue
2012
10.1109/SAMOS.2012.6404175
Embedded Computer Systems
Keywords
Field
DocType
embedded systems,field programmable gate arrays,graph theory,logic design,scheduling,FPGA designers,TaBit framework,bitstream generation,custom scheduling,embedded design,reconfigurable platform,software scheduling engine,task graph
Graph theory,Logic synthesis,Scheduling (computing),Computer science,Field-programmable gate array,Two-level scheduling,Software,Time to market,Bitstream,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4673-2296-6
0
0.34
References 
Authors
12
4
Name
Order
Citations
PageRank
Bonetto, A.100.34
Cazzaniga, A.2192.46
Durelli, G.C.300.68
Christian Pilato432932.19