Paper Info
Title
Design techniques for cross-layer resilience
Abstract
Current electronic systems implement reliability using only a few layers of the system stack, which simplifies the design of other layers but is becoming increasingly expensive over time. In contrast, cross-layer resilient systems, which distribute the responsibility for tolerating errors, device variation, and aging across the system stack, have the potential to provide the resilience required to implement reliable, high-performance, low-power systems in future fabrication processes at significantly lower cost. These systems can implement less-frequent resilience tasks in software to save power and chip area, can tune their reliability guarantees to the needs of applications, and can use the information available at each level in the system stack to optimize performance and power consumption. In this paper, we outline an approach to cross-layer system design that describes resilience as a set of tasks that systems must perform in order to detect and tolerate errors and variation. We then present strawman examples of how this task-based design process could be used to implement general-purpose computing and SoC systems, drawing on previous work and identifying key areas for future research.
Year
DOI
Venue
2010
10.1109/DATE.2010.5456960
Design, Automation & Test in Europe Conference & Exhibition
Keywords
Field
DocType
general purpose computers,logic design,optimisation,power consumption,reliability,system-on-chip,SoC systems,cross layer resilience design techniques,general purpose computing,performance optimize,power consumption,reliability,strawman examples
Psychological resilience,Logic synthesis,System on a chip,Computer science,Systems design,Real-time computing,Chip,Software,Design process,Statistical power
Conference
ISSN
ISBN
Citations 
1530-1591
978-1-4244-7054-9
28
PageRank 
References 
Authors
0.95
48
3
Name
Order
Citations
PageRank
Nicholas P. Carter134933.84
helia naeimi233823.24
Donald S. Gardner324536.33