Name
Title | ||
|---|---|---|
Evaluation of transition untestable faults using a multi-cycle capture test generation method |
Abstract | ||
|---|---|---|
Overtesting induces unnecessary yield loss of VLSIs. Untestable faults, which have no effect on the normal functions of circuits, may be detected in scan testing through scan chains. In this case, the detected untestable faults cause overtesting. Untestable faults consist of uncontrollable faults, unobservable faults, and uncontrollable and unobservable faults. Uncontrollable faults may be detected under invalid states through scan chains by shift-in operations. Unobservable faults cannot be observed at primary outputs, but their effects may be propagated to scan flip-flops. Thus, unobservable faults may be detected through scan chains by shift-out operations. Several methods to reduce the number of detected untestable faults have been proposed. These methods identify invalid states and generate test patterns to avoid invalid states. As a result, the number of detected uncontrollable faults are reduced. However, these methods cannot reduce the number of detected unobservable faults. In this paper, both uncontrollable and unobservable faults are identified using a multi-cycle capture test generation method. We evaluate the relationship between the numbers of untestable faults and the number of time expansions for ISCAS'89 benchmark circuits, and also evaluate factors to identify and classify untestable faults. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/DDECS.2010.5491771 | Design and Diagnostics of Electronic Circuits and Systems |
Keywords | Field | DocType |
VLSI,automatic test pattern generation,fault diagnosis,integrated circuit testing,VLSI yield loss,benchmark circuits,flip-flops,multicycle capture test generation method,transition untestable fault evaluation,uncontrollable fault detection | Automatic test pattern generation,Sequential logic,Computer science,Fault detection and isolation,Real-time computing,Test pattern generators,Electronic engineering,Electronic circuit,Unobservable,Very-large-scale integration,Reliability engineering | Conference |
ISSN | ISBN | Citations |
2334-3133 | 978-1-4244-6612-2 | 0 |
PageRank | References | Authors |
0.34 | 11 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masayoshi Yoshimura | 1 | 29 | 6.98 |
| Hiroshi Ogawa | 2 | 0 | 0.34 |
| Toshinori Hosokawa | 3 | 84 | 16.12 |
| Koji Yamazaki | 4 | 27 | 8.41 |