Name
Title | ||
|---|---|---|
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies |
Abstract | ||
|---|---|---|
Three-dimensional integrated circuits (3D-IC) have the potential to reduce interconnect length and improve performance especially in sub-65nm CMOS technologies. This paper describes design and performance analysis of the 3D-IC in sub-65nm CMOS technologies based on the accurate calculation of interconnects delays using 16-core processors as case studies. Performance improvement of the 3D-IC vs. 2D-IC is increased as CMOS scales down, which is consistent with the expected trend. The performance improvement is over 20%. Furthermore, performance of the 3D-IC in 65 nm (or 45 nm) CMOS technology is superior to that of the 2D-IC in 45 nm (or 32 nm) CMOS technology. It indicates that design conversion from 2D-IC to 3D-IC is superior to the CMOS technology migration according to COMS scaling. Reduction in repeater buffers and area overhead is also estimated. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISCAS.2010.5536963 | Circuits and Systems |
Keywords | Field | DocType |
CMOS integrated circuits,integrated circuit design,multiprocessing systems,performance evaluation,three-dimensional integrated circuits,3D-IC,CMOS technology,interconnect delay,multicore processor,performance analysis,size 65 nm,three dimensional integrated circuit | FO4,Computer science,CMOS,Electronic engineering,Integrated circuit design,Three-dimensional integrated circuit,Repeater,Interconnection,Integrated circuit,Performance improvement | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-5309-2 | 3 |
PageRank | References | Authors |
0.42 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nomura, K. | 1 | 3 | 1.09 |
| Abe, K. | 2 | 46 | 6.27 |
| Fujita, Shinobu | 3 | 46 | 2.35 |
| Kurosawa, Y. | 4 | 4 | 0.90 |