Name
Abstract | ||
|---|---|---|
DRAM cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh. Refresh operations contend with read operations, which increases read latency and reduces system performance. We show that eliminating latency penalty due to refresh can improve average performance by 7.2%. However, simply doing intelligent scheduling of refresh operations is ineffective at obtaining significant performance improvement. This paper provides an alternative and scalable option to reduce the latency penalty due to refresh. It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode. Therefore, a refresh operation has well defined points at which it can potentially be Paused to service a pending read request. Leveraging this property, we propose Refresh Pausing, a solution that is highly effective at alleviating the contention from refresh operations. It provides an average performance improvement of 5.1% for 8Gb devices, and becomes even more effective for future high-density technologies. We also show that Refresh Pausing significantly outperforms the recently proposed Elastic Refresh scheme. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/HPCA.2013.6522355 | High Performance Computer Architecture |
Keywords | Field | DocType |
DRAM chips,data integrity,performance evaluation,scheduling,DRAM cells,DRAM device,DRAM memory capacity,DRAM memory systems,DRAM rows,JEDEC-based distributed refresh mode,data integrity,elastic refresh scheme,high-density technologies,intelligent refresh operation scheduling,latency penalty,memory size 8 GByte,performance improvement,periodic refresh operations,read latency,read operations,read request,refresh pausing,system performance | Dram,Computer science,Scheduling (computing),Latency (engineering),Parallel computing,Dram memory,Real-time computing,Data integrity,Memory refresh,Embedded system,Scalability,Performance improvement | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-4673-5585-8 | 44 |
PageRank | References | Authors |
1.34 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prashant J. Nair | 1 | 346 | 15.74 |
| Chia-Chen Chou | 2 | 146 | 5.76 |
| Moinuddin K. Qureshi | 3 | 2639 | 110.61 |