| SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection | 1 | 0.35 | 2022 |
| Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking | 2 | 0.36 | 2022 |
| A Case for Emerging Memories in DNN Accelerators. | 0 | 0.34 | 2021 |
| ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches | 0 | 0.34 | 2020 |
| Thesaurus: Efficient Cache Compression via Dynamic Clustering | 1 | 0.34 | 2020 |
| SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM | 0 | 0.34 | 2019 |
| A Case for Multi-Programming Quantum Computers | 4 | 0.49 | 2019 |
| Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads | 0 | 0.34 | 2019 |
| SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories | 10 | 0.50 | 2018 |
| Morphable Counters - Enabling Compact Integrity Trees For Low-Overhead Secure Memories. | 11 | 0.51 | 2018 |
| Attaché - Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. | 2 | 0.35 | 2018 |
| Lisa: Increasing Internal Connectivity In Dram For Fast Data Movement And Low Latency | 0 | 0.34 | 2018 |
| Architectural Techniques to Enable Reliable and Scalable Memory Systems. | 0 | 0.34 | 2017 |
| DICE: Compressing DRAM Caches for Bandwidth and Capacity. | 4 | 0.37 | 2017 |
| Taming the instruction bandwidth of quantum computers via hardware-managed error correction. | 8 | 0.66 | 2017 |
| XED: Exposing On-Die Error Detection Information for Strong Memory Reliability. | 11 | 0.45 | 2016 |
| FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems. | 6 | 0.43 | 2016 |
| Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures | 5 | 0.40 | 2016 |
| Architectural Support for Mitigating Row Hammering in DRAM Memories | 32 | 1.33 | 2015 |
| Reducing Refresh Power in Mobile Devices with Morphable ECC | 9 | 0.44 | 2015 |
| AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems | 66 | 1.23 | 2015 |
| Reducing read latency of phase change memory via early read and Turbo Read | 18 | 0.70 | 2015 |
| DEUCE: Write-Efficient Encryption for Non-Volatile Memories | 33 | 0.98 | 2015 |
| Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures. | 13 | 0.53 | 2014 |
| Refresh pausing in DRAM memory systems | 13 | 0.55 | 2014 |
| A case for Refresh Pausing in DRAM memory systems | 44 | 1.34 | 2013 |
| ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates | 53 | 1.39 | 2013 |
