Name
Abstract | ||
|---|---|---|
A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TCSI.2013.2265961 | Circuits and Systems I: Regular Papers, IEEE Transactions |
Keywords | DocType | Volume |
CMOS integrated circuits,circuit noise,circuit tuning,elemental semiconductors,jitter,mean square error methods,millimetre wave integrated circuits,phase locked loops,silicon,silicon-on-insulator,voltage-controlled oscillators,PLL power consumption,RMS,SOI-CMOS PLL,Si,adaptive biasing scheme,adaptively biased VCO,frequency 23.5 GHz,frequency tuning,jitter,millimeter wave integrated circuit,power 27.2 mW,size 32 nm,Millimeter wave integrated circuits,phase locked loops,phase noise,silicon-on-insulator | Journal | 60 |
Issue | ISSN | Citations |
8 | 1549-8328 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Plouchart, J.-O. | 1 | 31 | 5.54 |
| Ferriss, M.A. | 2 | 0 | 0.34 |
| Natarajan, A.S. | 3 | 0 | 0.34 |
| Valdes-Garcia, A. | 4 | 1 | 1.07 |