Name
Abstract | ||
|---|---|---|
Asynchronous circuits are an attractive option to overcome many challenges currently faced by chip designers, such as increased process variation. However, the lack of CAD tools to generate asynchronous circuits limits the adoption of this promising technology. In this absence of CAD tools, the most time consuming part of chip design is the back-end (physical design) effort. We propose a complete design infrastructure to physically implement an asynchronous digital net list with orders of magnitude time savings over expert human effort. The core of this flow is the ability to generate customized logic that is compatible with available ASIC flows. We evaluate our flow against several asynchronous circuit benchmarks for which full custom physical implementations exist. Compared to hand-optimized custom designs, our flow produces layout that has, on average, a 51% area overhead, with a 12% increase in energy and a 9% increase in delay. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ASYNC.2013.27 | Asynchronous Circuits and Systems |
Keywords | Field | DocType |
application specific integrated circuits,asynchronous circuits,integrated circuit layout,logic design,ASIC flows,CAD tools,asynchronous circuit benchmarks,asynchronous digital net list,automated layout,cellTK,chip designers,customized logic,hand-optimized custom designs,increased process variation,nonstandard cells,physical design,Design Automation,Integrated Circuit Layout | Integrated circuit layout,Asynchronous communication,Computer architecture,Asynchronous system,Computer science,Application-specific integrated circuit,Full custom,Electronic design automation,Physical design,Asynchronous circuit,Embedded system | Conference |
ISSN | ISBN | Citations |
1522-8681 | 978-1-4673-5956-6 | 9 |
PageRank | References | Authors |
0.72 | 20 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert Karmazin | 1 | 27 | 1.87 |
| Carlos Tadeo Ortega Otero | 2 | 34 | 3.13 |
| Rajit Manohar | 3 | 1038 | 96.72 |