Name
Abstract | ||
|---|---|---|
A cell-based design flow for MTJ/MOS-hybrid logic circuits is presented towards the realization of practical-scale logic LSI based on nonvolatile logic-in-memory architecture. Newly-developed supplementary design tools including a precise MTJ device model enable to design MTJ/MOS-hybrid logic's intellectual properties (IPs) accurately. By the use of the IPs, various pattern layouts of the MOS and MTJ/MOS-hybrid logic-circuit cells can be automatically synthesized. The effectiveness of the proposed design flow is demonstrated through typical arithmetic-circuit design examples with a nonvolatile storage capability. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISCAS.2013.6571793 | Circuits and Systems |
Keywords | Field | DocType |
MIS devices,logic circuits,logic design,magnetic tunnelling,random-access storage,IP,MTJ device model,MTJ-MOS-hybrid logic intellectual properties,MTJ-MOS-hybrid logic-circuit cell-based design flow,arithmetic-circuit design,magnetic-tunnel-junction,newly-developed supplementary design tools,nonvolatile logic-in-memory LSI,practical-scale logic LSI | Logic synthesis,Hybrid logic,Logic gate,Pass transistor logic,Computer science,Circuit design,Electronic engineering,Design flow,Register-transfer level,Logic family,Computer hardware | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4673-5760-9 | 2 |
PageRank | References | Authors |
0.40 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masanori Natsui | 1 | 80 | 15.10 |
| Takahiro Hanyu | 2 | 441 | 78.58 |
| Noboru Sakimura | 3 | 116 | 22.07 |
| Tadahiko Sugibayashi | 4 | 127 | 28.40 |