Name
Title | ||
|---|---|---|
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit |
Abstract | ||
|---|---|---|
In this paper we propose a fully parallel 64K point radix-44 FFT processor. The radix-44 parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. The radix-44 block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. The resultant 64K point FFT processor shows significant reduction in intermediate memory but with increased hardware complexity. Compared to the state-of-art implementation [5], our architecture shows reduced latency with comparable throughput and area. The 64K point FFT architecture was synthesized using a 130nm CMOS technology which resulted in a throughput of 1.4 GSPS and latency of 47.7μs with a maximum clock frequency of 350MHz. When compared to [5], the latency is reduced by 303μs with 50.8% reduction in area. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISCAS.2013.6572518 | Circuits and Systems |
Keywords | Field | DocType |
CMOS integrated circuits,fast Fourier transforms,signal processing,CMOS technology,butterfly unit,frequency 350 MHz,hardware complexity,high throughput low latency memory,maximum clock frequency,optimized point FFT architecture,radix-44 block,temperature 64 K,wavelength 130 nm | Signal processing,Latency (engineering),Computer science,Parallel computing,Electronic engineering,CMOS,Fast Fourier transform,Supercomputer Education Research Centre,Latency (engineering),Throughput,Clock rate | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4673-5760-9 | 3 |
PageRank | References | Authors |
0.53 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Srikant Manas Kala | 1 | 41 | 10.27 |
| Nalesh, S. | 2 | 9 | 2.36 |
| Maity, A. | 3 | 3 | 0.53 |
| Nandy, S.K. | 4 | 43 | 7.29 |