Name
Title | ||
|---|---|---|
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor |
Abstract | ||
|---|---|---|
8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. Two types of electron injection scheme: both side injection scheme and self-repair one side injection scheme are analyzed comprehensively for 65nm technology node 8T-SRAM cell and also for 6T-SRAM cell. This paper shows that in the 6T-SRAM with the local injected electrons the read speed degrades by as much as 6.3 times. In contrast, the proposed 8T-SRAM cell with the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb, write disturb and read speed. In the proposed 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed scheme has no process or area penalty compared with the standard CMOS-process 8T-SRAM. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/CICC.2010.5617440 | Custom Integrated Circuits Conference |
Keywords | Field | DocType |
SRAM chips,half select disturb elimination,local injected electron asymmetric pass gate transistor,self-repair one side injection scheme,side injection scheme,size 65 nm,standard CMOS-process 8T-SRAM | Logic gate,Computer science,Electron injection,Electronic engineering,Static random-access memory,Pass gate,Transistor,Electrical engineering,Write margin,Electron | Conference |
ISSN | ISBN | Citations |
0886-5930 | 978-1-4244-5758-8 | 8 |
PageRank | References | Authors |
0.73 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Honda, K. | 1 | 8 | 0.73 |
| Kousuke Miyaji | 2 | 59 | 9.73 |
| Shuhei Tanakamaru | 3 | 121 | 18.35 |
| Miyano, S. | 4 | 10 | 1.52 |