Title
Runtime adaptation on dataflow HPC platforms
Abstract
We are facing an ever growing quest for performance in High Performance Computing (HPC) systems. The growing concerns for the power budgets and overall deployment costs required to run these systems are opening new ways to novel high performance computing platforms. New paradigms and architectures are being developed to tackle these challenges. In this context, FPGA-based HPC platforms employed to accelerate algorithms expressed as data flow programs are a promising paradigm. One traditional limiting factor of FPGA technology is that the ever increasing complexity of the applications might require the designer to switch to a bigger device or, conversely, the same device might be underutilized due to difficulties at sharing the available logic. Partial Reconfiguration is the standard technique to overcome such limitations. This paper presents the research work done during the technology transfer to extend the Maxeler design flow to efficiently support Partial Reconfiguration (PR). In this work we focus on the design and development of a methodology to support the PR feature in the Maxeler design flow, a commercially successful FPGA-based HPC platform, showing the advantages of such an approach on the resulting platform.
Year
DOI
Venue
2013
10.1109/AHS.2013.6604230
Adaptive Hardware and Systems
Keywords
Field
DocType
field programmable gate arrays,parallel processing,FPGA-based HPC platform,HPC system,Maxeler design flow,dataflow HPC platform,field programmable gate array,high performance computing,partial reconfiguration technique,runtime adaptation
Software deployment,Supercomputer,Computer science,Parallel computing,Technology transfer,Field-programmable gate array,Design flow,Real-time computing,Dataflow,Control reconfiguration,Data flow diagram,Embedded system
Conference
Citations 
PageRank 
References 
6
0.66
8
Authors
4
Name
Order
Citations
PageRank
Riccardo Cattaneo1579.14
Christian Pilato232932.19
Mastinu, M.360.66
Kadlcek, O.460.66