Name
Abstract | ||
|---|---|---|
This paper presents a digital scrambling technique to improve the linearity of flash time-to-digital converters (TDCs) with sub-gate-delay time resolution. Thanks to this approach, a flash TDC using N time arbiters behaves as a quasi-stochastic TDC with an equivalent number of samples equal to N2, at the negligible area cost of doubling the number of minimum load capacitors. The concept is proved in a 65-nm CMOS technology 40MHz TDC, which achieves a 3ps resolution. The differential nonlinearity is reduced from 1LSB to less than 0.2LSB. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ESSCIRC.2010.5619879 | Seville |
Keywords | DocType | ISSN |
cmos integrated circuits,asynchronous circuits,capacitors,convertors,cmos technology,digital linearization algorithm,digital scrambling technique,sub-gate-delay time resolution,time arbiters,time-to-digital converter,dynamic range,time to digital converter,linearity,adders,phase locked loops | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-4244-6662-7 | 9 | 1.09 |
References | Authors | |
3 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marco Zanuso | 1 | 152 | 14.89 |
| Salvatore Levantino | 2 | 351 | 43.23 |
| alberto puggelli | 3 | 9 | 1.09 |
| Carlo Samori | 4 | 349 | 39.76 |
| Andrea L. Lacaita | 5 | 320 | 42.41 |