Title
3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS
Abstract
A Karatsuba-based 64b Galois field multiplier for on-die acceleration of public-key encryption is fabricated in 1.1V, 45nm CMOS and occupies 0.021mm2. 2-level Karatsuba design using interleaved 32b multipliers and folded datapath organization results in single-cycle latency at 3GHz operation with total power consumption of 74mW and 32% area reduction over conventional multipliers, resulting in 3.2x speedup of Diffie-Helman key exchange workloads.
Year
DOI
Venue
2010
10.1109/ESSCIRC.2010.5619895
Seville
Keywords
DocType
ISSN
cmos integrated circuits,galois fields,public key cryptography,2-level karatsuba 64b galois field multiplier,2-level karatsuba design,cmos,diffie-helman key exchange workloads,folded datapath,frequency 3 ghz,interleaved 32b multipliers,on-die acceleration,power 74 mw,public-key encryption acceleration,size 45 nm,public key,key exchange,encryption,galois field,public key encryption,acceleration
Conference
1930-8833
ISBN
Citations 
PageRank 
978-1-4244-6662-7
1
0.35
References 
Authors
3
9
Name
Order
Citations
PageRank
S. Mathew146276.59
Michael E. Kounavis226525.14
Farhana Sheikh315822.03
S. K. Hsu452152.06
amit agarwal561.24
Himanshu Kaul645651.07
Mark A. Anders718517.43
Frank L. Berry8312.82
Ram Krishnamurthy965074.63