Name
Abstract | ||
|---|---|---|
The ever growing demand for functionally robust and error-free industrial electronics necessitates the development of techniques that will prohibit the propagation of functional errors to the final tape-out stage. This paramount requirement in the semiconductor world is imposed by the equivocal observation that functional errors slipping to silicon production introduce immense amounts of cost and jeopardize chip release dates. Functional verification and debugging are burdened with the tedious task of guaranteeing logic functionality early in the design cycle. In this paper, we present an automated method for the very first stage of functional debugging, called failure triage. Failure triage is the task of analyzing large sets of failures, grouping together those that are likely to be caused by the same design error, and then allocating those groups to the appropriate engineers for fixing. The introduced framework instruments techniques from the machine learning domain combined with the root cause analysis power of modern SAT-based debugging tools, in order to exploit information from error traces and bin the corresponding failures using clustering algorithms. Preliminary experimental results indicate an average accuracy of 93 % for the proposed failure triage engine, which corresponds to a 43 % improvement over conventional automated methods. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/IOLTS.2013.6604054 | On-Line Testing Symposium |
Keywords | Field | DocType |
computability,electronic engineering computing,failure analysis,integrated circuit design,integrated circuit testing,learning (artificial intelligence),monolithic integrated circuits,pattern clustering,SAT-based debugging tools,automated functional debugging method,clustering algorithms,design cycle,error trace signature extraction,error-free industrial electronics,failure triage engine,functional error propagation,functional verification,functionally robust industrial electronics,instrument techniques,logic functionality,machine learning domain,root cause analysis,silicon production,Clustering,Design Debugging,Failure Triage,Regression Tests | Functional verification,Computer science,Root cause analysis,Computability,Electronic engineering,Exploit,Real-time computing,Integrated circuit design,Triage,Cluster analysis,Reliability engineering,Debugging | Conference |
ISSN | Citations | PageRank |
1942-9398 | 2 | 0.38 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zissis Poulos | 1 | 66 | 9.30 |
| Yu-Shen Yang | 2 | 92 | 8.23 |
| A. Veneris | 3 | 937 | 67.52 |