Paper Info
Title
Out-of-order retirement of instructions in sequentially consistent multiprocessors
Abstract
Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking effects in the reorder buffer (ROB). Wide instruction windows are very beneficial to multiprocessors that implement a strict memory model, especially when both loads and stores encounter long latencies due to cache misses, and whose stalls must be overlapped with instruction execution to overcome the memory gap. In this paper, the Validation Buffer (VB) multiprocessor architecture is proposed as a cost-effective, checkpoint-free, scalable approach to retire instructions out of program order, while still enforcing sequential consistency, and without impacting the memory hierarchy or interconnect. Experimental results show that utilizing the Validation Buffer can speed up both release and sequentially consistent in-order retirement in future multiprocessor systems by between 3% and 20%, depending on the ROB size.
Year
DOI
Venue
2010
10.1109/ICCD.2010.5647558
Computer Design
Keywords
Field
DocType
buffer storage,instruction sets,memory architecture,multiprocessing systems,processor scheduling,head of line blocking effect,inflight instruction,instruction execution,memory gap,multiprocessor architecture,out of order retirement,pipeline stall,reorder buffer,runtime scheduling,sequentially consistent multiprocessor,strict memory model,validation buffer
Sequential consistency,Memory hierarchy,Instruction set,Computer science,Cache,Parallel computing,Real-time computing,Multi-core processor,Out-of-order execution,Memory architecture,Re-order buffer,Embedded system
Conference
ISSN
ISBN
Citations 
1063-6404
978-1-4244-8936-7
1
PageRank 
References 
Authors
0.35
13
4
Name
Order
Citations
PageRank
Rafael Ubal132216.93
J. Sahuquillo2434.02
S. Petit31369.31
Pedro Lopez438727.39