S. Petit - Citegraph

Author Info

Name	Affiliation	Papers
S. PETIT	Departmento de Inforática de Sistemas y Computadores, Universidad Politécnica de Valencia, Valencia, Spain	15
Collaborators	Citations	PageRank
19	136	9.31
Referers	Referees	References
373	355	170

Search Limit

100373

Publications (15 rows)

Collaborators (19 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Design of Hybrid Second-Level Caches	5	0.42	2015
Efficient Register Renaming and Recovery for High-Performance Processors	2	0.40	2014
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches	5	0.49	2012
Out-of-order retirement of instructions in sequentially consistent multiprocessors	1	0.35	2010
Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors	0	0.34	2009
A simple power-aware scheduling for multicore systems when running real-time applications	28	1.56	2008
Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot	2	0.38	2008
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors	84	2.73	2007
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors	2	0.37	2007
RACFP: a training tool to work with floating-point representation, algorithms, and circuits in undergraduate courses	1	0.41	2006
Applying the zeros switch-off technique to reduce static energy in data caches	1	0.36	2006
Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors	1	0.35	2005
A comparison study of the HLRC-DU protocol versus a HLRC hardware assisted protocol	1	0.35	2005
Characterizing parallel workloads to reduce multiple writer overhead in shared virtual memory systems	0	0.34	2002
LIDE: a simulation environment for shared virtual memory systems	3	0.45	2000

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