Name
Title | ||
|---|---|---|
Efficient vlsi implementation of reduced-state sequence estimation for wireless communications |
Abstract | ||
|---|---|---|
Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to greatly reduce computational complexity, such that efficient RSSE architectures can be derived. As a proof of concept, an RSSE was implemented in dedicated hardware, that achieves a 1.6 times higher hardware efficiency when compared to prior art. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICASSP.2013.6638111 | Acoustics, Speech and Signal Processing |
Keywords | Field | DocType |
VLSI,computational complexity,equalisers,wireless channels,RSSE,VLSI implementation,channel equalizer,computational complexity,reduced-state sequence estimation,wireless communications,Channel equalization,Design space exploration,Evolved EDGE,RSSE,VLSI implementation | Design space,Mathematical optimization,Wireless,State sequence,Computer science,Real-time computing,Implementation,Proof of concept,Computer engineering,Very-large-scale integration,Design space exploration,Computational complexity theory | Conference |
ISSN | Citations | PageRank |
1520-6149 | 0 | 0.34 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stefan Zwicky | 1 | 9 | 1.70 |
| Christian Benkeser | 2 | 64 | 7.86 |
| A. Burg | 3 | 1426 | 126.54 |
| Qiuting Huang | 4 | 399 | 145.90 |