Name
Abstract | ||
|---|---|---|
This paper addresses the power consumption in CMOS logic gates through a study that considers the transistor network arrangement and the advance of the technology node. The relationship between charge/discharge and short-circuit dynamic power components are investigated through electrical simulations (SPICE). The static power dissipation is also analyzed. Experimental results demonstrate that dynamic power still remains the main source of consumption in standard cell designs, although the short-circuit component seems to decrease at the advancing of CMOS fabrication processes. The static power, on the other hand, keeps growing at each new technology node, becoming even more a critical challenge in VLSI design. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/SBCCI.2013.6644863 | Integrated Circuits and Systems Design |
Keywords | Field | DocType |
CMOS digital integrated circuits,VLSI,integrated circuit design,logic gates,CMOS fabrication processes,CMOS logic gates,SPICE,VLSI design,electrical simulations,power consumption analysis,short-circuit dynamic power components,standard cell designs,static CMOS gates,static power dissipation,transistor network arrangement,CMOS,Digital circuit,logic gate,power dissipation,short-circuit | Power optimization,Pass transistor logic,Computer science,Adiabatic circuit,Electronic engineering,CMOS,Dynamic demand,Depletion-load NMOS logic,Logic family,Integrated injection logic,Electrical engineering | Conference |
Citations | PageRank | References |
3 | 0.39 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alberto Wiltgen | 1 | 3 | 0.39 |
| Kim A. Escobar | 2 | 3 | 0.73 |
| Andre Inacio Reis | 3 | 23 | 3.79 |
| Renato P. Ribas | 4 | 204 | 33.52 |