Name
Abstract | ||
|---|---|---|
The significance of redundant technologies for improving dependability and delay fault testability are growing. So, delay fault testing on two-rail logic circuits well known as a class of redundant technologies will become important. Two-rail logic circuits can be efficiently tested by noncodeword vector pairs. However, noncodeword vector pairs may sensitize some faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with noncodeword vector pairs may be overtesting. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the overtesting. The amounts of test data for the proposed test sets are, on average, 28.2 percent less than those for the test sets, which are obtained by the existing construction for unate circuits and lead to the overtesting. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TC.2010.230 | Computers, IEEE Transactions |
Keywords | Field | DocType |
delay circuits,fault tolerant computing,logic circuits,logic testing,delay fault testability,fault secure property,noncodeword vector pair,redundant technology,robust path delay fault testing,test data,test sets,two-rail logic circuit,Two-rail logic circuit,monotone function,overtesting.,path delay fault testing,testability | Testability,Stuck-at fault,Dependability,Logic gate,Computer science,Real-time computing,Robustness (computer science),Combinational logic,Test data,Electronic circuit | Journal |
Volume | Issue | ISSN |
60 | 10 | 0018-9340 |
Citations | PageRank | References |
1 | 0.35 | 13 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuteru Namba | 1 | 114 | 27.93 |
| Hideo Ito | 2 | 100 | 17.45 |