Name
Abstract | ||
|---|---|---|
Constructed from a current reused architecture for low power consumption, a cascode topology of an LC VCO and a divide-by-4 prescaler is used in a PLL. In the prescaler, the first-stage divide-by-2 divider is an injection locking circuit used to frequency lock to an incident signal to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. Implemented with 1.8-V 0.18-μm CMOS, the PLL provides the phase noise of -121.67 dBc/Hz at 1-MHz offset and consumes 3.4 mW at 2.4 GHz. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ESSCIRC.2013.6649070 | ESSCIRC |
Keywords | DocType | ISSN |
cmos integrated circuits,frequency synthesizers,low-power electronics,network topology,phase locked loops,voltage-controlled oscillators,cmos,d-type filpflop,lc vco,pll,cascode topology,current reused architecture,divide-by-2 divider,frequency 2.3 ghz to 2.7 ghz,frequency synthesizer,injection locking circuit,low power consumption,power 3.4 mw,size 0.18 mum,low power electronics | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-4799-0643-7 | 0 | 0.34 |
References | Authors | |
5 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chih-Hsiang Chang | 1 | 103 | 10.91 |
| Ching-Yuan Yang | 2 | 227 | 36.15 |
| Yu Lee | 3 | 11 | 3.21 |
| junhong weng | 4 | 0 | 0.68 |
| naichen cheng | 5 | 0 | 0.34 |