Title
Built-in Self-Repair in a 3D die stack using programmable logic
Abstract
3D stacked integrated circuits hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacture of these devices. We propose helping to mitigate these issues by repairing the stack with programmable logic in FPGAs that have already been included in the stack for other purposes. Specifically, we propose bypassing the defective portion of a die by replacing the defective functionality with functionality on the FPGA. In this paper, we focus on the replacement of selected defective functional units in an out-of-order microprocessor. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.
Year
DOI
Venue
2013
10.1109/DFT.2013.6653613
Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Keywords
Field
DocType
built-in self test,field programmable gate arrays,microassembling,microprocessor chips,programmable logic devices,three-dimensional integrated circuits,3D die stack,3D stacked integrated circuits,FPGA,built-in self-repair,defective functionality,defective partition,original defective copy,out-of-order microprocessor,programmable logic,selected defective functional units,system performance
Erasable programmable logic device,Computer science,Programmable Array Logic,Programmable logic array,Microprocessor,Simple programmable logic device,Field-programmable gate array,Electronic engineering,Embedded system,Programmable logic device,Macrocell array
Conference
ISSN
ISBN
Citations 
1550-5774
978-1-4799-1583-5
1
PageRank 
References 
Authors
0.36
14
4
Name
Order
Citations
PageRank
K. Nepal19610.42
Shen, X.210.36
Jennifer Dworak313211.63
Manikas, T.410.36