Name
Abstract | ||
|---|---|---|
Using functional test for Fmax analysis is still the only effective method used in practice in spite of the fact that the test cost associated with functional Fmax test remains to be a major problem. In this paper, we develop novel design-for-testability (DFT) structures to considerably reduce the cost of initializing the circuit during functional test. The proposed architectures take advantage of existing DFT structures to reduce the overall cost of hardware and have no impact on the circuit timing. Our implementations of these DFT structures for initializing ITC'99 benchmark circuit b19 demonstrate the effectiveness of these techniques in reducing test time and thus the overall test cost. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCD.2013.6657017 | Computer Design |
Keywords | DocType | Citations |
circuit testing,design for testability,DFT,ITC'99 benchmark circuit b19,circuit initialization,design-for-testability,functional Fmax test-time reduction,Compression,Design for Testability,Functional Fmax,Initialization | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ujjwal Guin | 1 | 219 | 18.96 |
| Tapan J. Chakraborty | 2 | 258 | 26.11 |
| Mohammad Tehranipoor | 3 | 3181 | 243.40 |