Name
Abstract | ||
|---|---|---|
We propose a floating-point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in these devices. We propose a format that reduces the variable shifter penalty. It is based on a radix-64 representation such that the number of the possible shifts is considerably reduced. Thus, the execution time of the floating-point addition is highly optimized when it is performed in an FPGA device, which compensates for the multiplication penalty when a high radix is used, as experimental results have shown. Consequently, the main problem of previous specific high-radix FPGA designs (no speedup for codes with a balanced number of multiplications and additions) is overcome with our proposal. The inherent architecture supporting the new format works with greater bit precision than the corresponding single precision (SP) IEEE-754 standard. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCD.2013.6657053 | Computer Design |
Keywords | Field | DocType |
field programmable gate arrays,floating point arithmetic,logic design,FPGA device,arithmetic operation,balanced code,floating point addition,floating point representation,high-radix FPGA design,radix-64 representation,variable shift operation,variable shifter penalty,FPGA devices,Floating Point representation,high radix arithmetic,variable shifts | Single-precision floating-point format,Logic synthesis,Fixed-point arithmetic,Floating point,Computer science,Double-precision floating-point format,Parallel computing,Field-programmable gate array,Multiplication,Speedup | Conference |
Citations | PageRank | References |
2 | 0.40 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Julio Villalba | 1 | 219 | 23.56 |
| Javier Hormigo | 2 | 113 | 19.45 |
| Corbera, F. | 3 | 2 | 0.40 |
| Gonzalez, M. | 4 | 29 | 1.97 |