Name
Abstract | ||
|---|---|---|
One decade after their introduction into wireless applications, digital fractional-N phase-locked loops are becoming a competitive solution for products. Their ultimate level of spurs is often bounded by the resolution and the linearity of the time-to-digital converter. Although methods for mitigating its nonlinearity have been proven effective in lowering spurs, they typically increase the level of random noise. By contrast, digital-PLL architectures based on digital-to-time converters enable nonlinearity cancellation and spur reduction with no penalty on noise level, while reducing design complexity and power consumption. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/CICC.2013.6658472 | Custom Integrated Circuits Conference |
Keywords | Field | DocType |
linearisation techniques,phase locked loops,time-digital conversion,design complexity reduction,digital PLL,digital fractional-N phase locked loop,nonlinearity cancellation,power consumption reduction,spur reduction,time-digital converter linearity,time-digital converter resolution,wireless application | Phase-locked loop,Nonlinear system,Wireless,Computer science,Linearity,Noise level,Spur,Converters,Control engineering,Electronic engineering,Bounded function | Conference |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Salvatore Levantino | 1 | 351 | 43.23 |
| Carlo Samori | 2 | 349 | 39.76 |