Title
A variation tolerant architecture for ultra low power multi-processor cluster
Abstract
Process and environmental temperature variations have a detrimental effect on performance and reliability of modern embedded systems. This sensitivity to operating conditions significantly increases in ultra-low-power (ULP) devices and in all those applications that rely on reduced supply voltage to achieve energy efficiency. We propose a lightweight runtime solution to tolerate process and environmental temperature variations. The novelty of our solution is the ability to tackle both hold time and setup time sensitivity to variations by dynamically adapting latencies of the datapaths without compromising execution correctness. We extensively tested our solution evaluating the trade-offs, demonstrating the cost, performance, reliability gain compared to state-of-the-art static solutions. The proposed solution is able to reach a performance gain up to 30% with a very low (≈ 4%) area overhead.
Year
DOI
Venue
2013
10.1109/PATMOS.2013.6662152
Power and Timing Modeling, Optimization and Simulation
Keywords
Field
DocType
flip-flops,integrated circuit reliability,low-power electronics,multiprocessing systems,ULP devices,datapath dynamically-adapting latency,detrimental effect,embedded system reliability,energy efficiency,environmental temperature variation,flip-flops,hold time,process variation,reliability gain,setup time sensitivity,supply voltage,ultralow-power multiprocessor cluster,variation tolerant architecture
Architecture,Multi processor,Computer science,Efficient energy use,Correctness,Voltage,Real-time computing,Electronic engineering,Novelty,Environmental temperature,Embedded system,Low-power electronics
Conference
ISSN
Citations 
PageRank 
2474-5456
0
0.34
References 
Authors
0
4
Name
Order
Citations
PageRank
Daniele Bortolotti1757.13
Davide Rossi241647.47
Andrea Bartolini345751.90
Luca Benini4131161188.49