Name
Abstract | ||
|---|---|---|
Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ATS.2013.23 | Asian Test Symposium |
Keywords | Field | DocType |
fault diagnosis,integrated circuit testing,ISCAS'89 benchmark circuit,deep submicron technology,high density integrated circuit,metal layer,resistive open fault,small delay fault simulation,fault diagnosis,fault simulation,resistive open faults,small delay faults | Stuck-at fault,Resistive touchscreen,Computer science,Signal transition,Real-time computing,Electronic engineering,Fault (power engineering),Fault Simulator,Electronic circuit,Integrated circuit,Fault indicator | Conference |
ISSN | Citations | PageRank |
1081-7735 | 1 | 0.37 |
References | Authors | |
10 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Koji Yamazaki | 1 | 27 | 8.41 |
| Toshiyuki Tsutsumi | 2 | 59 | 7.28 |
| Hiromitsu Takahashi | 3 | 2 | 0.78 |
| Higami, Y. | 4 | 5 | 1.35 |