Name
Title | ||
|---|---|---|
A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers |
Abstract | ||
|---|---|---|
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation of the generated timing was 34% smaller than that with a conventional technique and cycle time was reduced by 16% at the supply voltage of 0.6V in 40nm CMOS technology with this scheme. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASSCC.2010.5716633 | Solid State Circuits Conference |
Keywords | DocType | Volume |
cmos memory circuits,sram chips,amplifiers,timing,cmos technology,sram sense amplifiers,digitized replica bitline delay technique,random-variation-tolerant timing generation,sense timing variation,size 40 nm,transistor threshold voltage,voltage 0.6 v,random variation,static random access memory,monte carlo method,cmos integrated circuits,monte carlo methods,threshold voltage | Journal | 46 |
Issue | ISBN | Citations |
11 | 978-1-4244-8300-6 | 12 |
PageRank | References | Authors |
0.82 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yusuke Niki | 1 | 44 | 5.58 |
| Atsushi Kawasumi | 2 | 153 | 19.91 |
| azuma suzuki | 3 | 12 | 0.82 |
| Yasuhisa Takeyama | 4 | 86 | 11.06 |
| Osamu Hirabayashi | 5 | 76 | 10.08 |
| Keiichi Kushida | 6 | 61 | 4.86 |
| Fumihiko Tachibana | 7 | 37 | 5.98 |
| Yuki Fujimura | 8 | 34 | 3.88 |
| Tomoaki Yabe | 9 | 86 | 11.09 |