Name
Abstract | ||
|---|---|---|
Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach. In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/FPT.2013.6718394 | Field-Programmable Technology |
Keywords | Field | DocType |
DRAM chips,cryptography,field programmable gate arrays,logic design,AES key schedule,DRAM chips,DRAM contents,FPGA-accelerated key search,FPGA-based architecture,Maxeler dataflow computing system,RAM modules,attack vector,bit error model,cold-attacks,cold-boot attacks,cryptographic applications,cryptographic structure,custom computing machines,decayed cryptographic keys,decrypted keys,error rate,key data,memory image size,nonvolatile memory,software implementation,target computer | Reboot,Cold boot attack,Computer science,Cryptography,Real-time computing,Computer hardware,Key (cryptography),CAS latency,Cipher,Key schedule,Parallel computing,Memory rank,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4799-2199-7 | 2 | 0.38 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Heinrich Riebler | 1 | 13 | 3.58 |
| Tobias Kenter | 2 | 13 | 6.07 |
| Christoph Sorge | 3 | 172 | 22.16 |
| Christian Plessl | 4 | 297 | 35.98 |