Title
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator
Abstract
In this brief, a new technique to measure the on-chip rise/fall delay of an individual gate is presented. In the proposed technique, the rise/fall gate delay is measured using the duty cycle of a reconfigurable ring oscillator (RRO). A set of linear equations is formed with the different configuration settings of the RRO, relating the rise/fall delay of all the gates in the path of the RRO to the positive/negative duty cycle of the undivided RRO. The high-frequency undivided RRO signal is needed for this type of measurement as it preserves the rise/fall delay of an individual gate. However, it is difficult to bring the high-frequency undivided RRO signal outside the chip due to the frequency limitation of the output pad. The high-frequency RRO signal is subsampled by a clock that is generated from an on-chip phase-locked loop to make it low frequency. The rise and fall delays of an individual gate can be calculated from the difference of the duty cycle of the subsampled RRO signal at two different configurations of the RRO. The proposed concept is validated in a test chip that is fabricated in an industrial 65-nm technology node.
Year
DOI
Venue
2014
10.1109/TCSII.2013.2296118
Circuits and Systems II: Express Briefs, IEEE Transactions
Keywords
Field
DocType
delays,integrated circuit measurement,integrated circuit reliability,negative bias temperature instability,oscillators,phase locked loops,configuration settings,frequency limitation,high-frequency undivided RRO signal,linear equations,on-chip measurement,on-chip phase-locked loop,on-chip rise/fall delay,positive/negative duty cycle,reconfigurable ring oscillator,rise/fall gate delay,size 65 nm,Duty cycle,on-chip measurement of rise/fall gate delay,reconfigurable ring oscillator (RRO),subsampling technique
Phase-locked loop,Low frequency,Ring oscillator,Oscillation,Duty cycle,Control theory,Chip,Electronic engineering,Negative-bias temperature instability,Electrical engineering,Mathematics
Journal
Volume
Issue
ISSN
61
3
1549-7747
Citations 
PageRank 
References 
0
0.34
6
Authors
2
Name
Order
Citations
PageRank
Bishnu Prasad Das100.68
Hidetoshi Onodera2455105.29